Trade Assurance E-ENERGY HOLDING LIMITED
With over 17 years of IT hardware supply chain resources

IntelGrandRidgePlatformWillFeature24AtomCoresBasedOn7nmHLL+Process–E-ENERGYHOLDINGLIMITED

News

 

A slide of Intel’s upcoming Grand Ridge platform has leaked out courtesy of AdoredTv’s OverVolted podcast. With Grand Ridge platform, Intel is planning to introduce an atom processor with up to 24 cores glued together by Scalable Coherent Fabric. Grand Ridge will expand the company’s portfolio on the Atom side and will feature the new Gracemont architecture.

Intel’s Grand Ridge platform: 24 Cores based on Gracemont, DDR5, PCIe 4.0 and 7nm HLL+

Gracemont architecture was originally intended to be introduced in 2021 and is equivalent to the Golden Cove architecture on desktop (which succeeds Willow Cove).  It will be the first update since the dated Tremont architecture and will represent a massive leap in IPC and overall compute in the low power segments. It also features support for DDR5 memory and PCIe 4.0 so is pretty “futureproof”. It will be able to boost up to 2.6GHz which is pretty fast for an Atom processor and can support RAM clocked at 5.6 Ghz.

Marvel’s Avengers Offers More Exclusive Content Through Verizon, Virgin, Intel, and 5 Gum

The complete package will measure 47.5mm x 47.5mm and be fabricated on the Intel 7nm (HLL+) process. The HLL+ designation is very interesting and as of right now we are not sure what this indicates. Intel’s Raja Koduri is getting ready to deliver key updates on the 13th of August and I am sure we will get more details on this front then.

UDIMM and SODIMM memory types are both supported and niche specializations such as packet processing, flow distribution, flexible processing pipeline, transmit scheduler, and security processor are included in the SOC as well. It appears to feature new instruction sets as well with a 64KB iCache, 32KB dCache, and a 4MB L2 cluster (which I assume is shared across all cores). The platform can support 4x USB 3.1, 4x USB 2.0, I3C, eSPI, MDIO, UIART, SMBus and I2C.

[Speculation] It is unclear whether the delay in 7nm affects this product. Because of the HLL+ designation we are not entirely sure as this could constitute a risk production of some sort. If that is the case then this slide is clearly a few months old and could be outdated. We will try and procure some new slides but in the meantime, it is very interesting to see Intel transition towards a high core count approach in all its products.  [/speculation].

Prev:

Next:

Leave a message