It was a cold day in London, 2018 when we witnessed the AMD EPYC Embedded 3000 Series Launch. While we were able to test the AMD EPYC 3251 a few months after, that was an 8-core part, not a 12 or 16 core part that occupied the top-end of the stack. Our readers asked questions, as did we. Starting in late November 2019, the top-end dual-die EPYC 3000 parts started shipping in volume and we have been working to get one ever since. We can now bring you the fruits of those efforts, a review of the AMD EPYC 3451 16-core embedded processor. This is a dual die EPYC design from the Naples generation with several features that we wanted to cover in our review.huh721010al5200
AMD EPYC 3451 and EPYC 3001 Series Platform Video
Since this is a push in the new year, we have a video discussing a good portion of what is covered in this review.
Check it out if you just wanted to learn about the EPYC 3451 and the EPYC Embedded 3001 series. Of course, we go into more detail in this piece.
AMD EPYC 3451 Overview
Key stats for the AMD EPYC 3451: 16 cores / 32 threads with a 2.14GHz base clock, 2.45GHz all-core boost, and a maximum 3.0GHz turbo boost. There is 32MB of onboard L3 cache. The CPU features a configurable 80-100W TDP. These are $778 list price parts.
Here is the lscpu output for the AMD EPYC 3451:
You will notice a few changes from the launch of the part. The 2.14GHz base clock is 10MHz lower than the original spec. We covered how this became a configurable TDP part as in our AMD EPYC 3000 Line Gets Updated Adding and Dropping Models piece. We also see list pricing that is $102 lower than we had on the original slide:
Most of those changes are more like a refinement of the stack especially since we have seen the “Rome” launch on the socketed server-side in the interim.
Since the AMD EPYC 3451 has a “1” as the last digit, we know that it is a “Naples” generation part. We also know that this is a dual-die part with two 8 core CCDs. As a result, this system has two distinct NUMA nodes, much like a two-socket 8-core system:
On one hand, Intel Xeon D parts in this space only have a single NUMA node currently. Another way to look at the two die solution is that it is much more familiar setup to many segments than the four NUMA node EPYC 7001 CPU.
Having a two-die solution is extremely important. This gives the system up to 64x PCIe Gen3 lanes. The Intel Xeon D-1500 / Xeon D-1600 has 24x PCIe Gen3 lanes and 8x Gen2 lanes while the Intel Xeon D-2100 series gets 32 PCIe Gen3 dedicated lanes plus 20 HSIO lanes where some can be configured for PCIe in a system. While the single die EPYC 3000 series competes directly with the Xeon D-1500/ D-1600 and offers more performance, the dual die offers something even bigger. Indeed, the dual die AMD EPYC 3451 offers more PCIe lanes than a single-socket Intel Xeon Scalable server (48) which is great when one needs NICs, accelerators, and storage.
We previously tested the Intel Xeon D-2183IT and found it to be a very capable part with 16 cores, quad-channel DDR4-2400, and a 100W TDP. That makes it a direct competitor to the EPYC 3451 across a lot of features. There is one big difference, and that is price. MSRP for the Intel Xeon D-2183IT is $1764 which puts it roughly $1000 more or about a 125% premium over the EPYC 3451. In our review, we are going to see if it is worth that kind of premium.
For this testing we are using the updated AMD Wallaby platform:
- System: AMD Wallaby
- CPU: 1x AMD EPYC 3451 16-core
- Memory: 4x 16GB DDR4-2666 DDR4 DRAM
- OS SSD: 1x Intel DC S3710 400GB Boot
Some of the major updates here are that we get more PCIe and network slots. With the dual-die configuration, we get up to 64 PCIe lanes and up to 8x 10GbE ports, 32 lanes and 4 ports per-die.
The Wallaby platform exposes some, but not all of those features. It does, however, expose more than the version we used for the EPYC 3251 testing and, importantly, has the dual die part along with quad-channel DDR4-2666 memory support. We usually prefer using production boards from a partner, but for embedded products, we often have to use reference platforms.
Next, it is time to get to our benchmarks.